Two-dimensional bit-stuffing schemes with multiple transformers

Sharon Aviran, Paul H. Siegel, Jack K. Wolf

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

We present bit-stuffing schemes which encode arbitrary data sequences into two-dimensional (2-D) constrained arrays. We consider the class of 2-D runlength-limited (RLL) (d, ∞) constraints as well as the 'no isolated bits' (n.i.b.) constraint, both defined on the square lattice. The bit stuffing technique was previously introduced and applied to the class of 2-D (d, ∞) constraints. Analytical lower bounds on the rate of these encoders were derived. For d = 1, a more general scheme was analyzed and shown to obtain improved performance. We extend the (1, ∞)-construction to (d, ∞) constraints where d ≥ 2. We then suggest a bit-stuffing scheme for the n.i.b. constraint, based on a capacity-achieving scheme for a one-dimensional RLL (0, 3) constraint. Simulation results demonstrate the performance of the proposed schemes.

Original languageEnglish (US)
Title of host publicationProceedings of the 2005 IEEE International Symposium on Information Theory, ISIT 05
Pages1478-1482
Number of pages5
Volume2005
DOIs
StatePublished - Dec 1 2005
Event2005 IEEE International Symposium on Information Theory, ISIT 05 - Adelaide, Australia
Duration: Sep 4 2005Sep 9 2005

Other

Other2005 IEEE International Symposium on Information Theory, ISIT 05
CountryAustralia
CityAdelaide
Period9/4/059/9/05

Fingerprint

Transformer
Run Length
Encoder
Square Lattice
Lower bound
Arbitrary
Demonstrate
Simulation

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Information Systems
  • Modeling and Simulation
  • Applied Mathematics

Cite this

Aviran, S., Siegel, P. H., & Wolf, J. K. (2005). Two-dimensional bit-stuffing schemes with multiple transformers. In Proceedings of the 2005 IEEE International Symposium on Information Theory, ISIT 05 (Vol. 2005, pp. 1478-1482). [1523589] https://doi.org/10.1109/ISIT.2005.1523589

Two-dimensional bit-stuffing schemes with multiple transformers. / Aviran, Sharon; Siegel, Paul H.; Wolf, Jack K.

Proceedings of the 2005 IEEE International Symposium on Information Theory, ISIT 05. Vol. 2005 2005. p. 1478-1482 1523589.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Aviran, S, Siegel, PH & Wolf, JK 2005, Two-dimensional bit-stuffing schemes with multiple transformers. in Proceedings of the 2005 IEEE International Symposium on Information Theory, ISIT 05. vol. 2005, 1523589, pp. 1478-1482, 2005 IEEE International Symposium on Information Theory, ISIT 05, Adelaide, Australia, 9/4/05. https://doi.org/10.1109/ISIT.2005.1523589
Aviran S, Siegel PH, Wolf JK. Two-dimensional bit-stuffing schemes with multiple transformers. In Proceedings of the 2005 IEEE International Symposium on Information Theory, ISIT 05. Vol. 2005. 2005. p. 1478-1482. 1523589 https://doi.org/10.1109/ISIT.2005.1523589
Aviran, Sharon ; Siegel, Paul H. ; Wolf, Jack K. / Two-dimensional bit-stuffing schemes with multiple transformers. Proceedings of the 2005 IEEE International Symposium on Information Theory, ISIT 05. Vol. 2005 2005. pp. 1478-1482
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