Abstract
While the high performance computing (HPC) community is relying on simulations increasingly to co-design and optimize HPC interconnects, the simulation community lacks a coherent set of practices to be followed when validating the simulators and network models. Validation of HPC network simulation models is a multi-step process starting with the selection of representative communication patterns, configuring the network model, followed by designing the set of experiments, and finally, documenting the outcome for reproducibility. In this paper, we present a set of recommended practices for each of these steps in the validation process. If the recommendations are followed, the end result should be a validated network model that can make reasonably accurate predictions and convince the community about the correctness of the model.
Original language | English (US) |
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Title of host publication | 2017 Winter Simulation Conference, WSC 2017 |
Editors | Victor Chan |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 659-674 |
Number of pages | 16 |
ISBN (Electronic) | 9781538634288 |
DOIs | |
State | Published - Jan 4 2018 |
Event | 2017 Winter Simulation Conference, WSC 2017 - Las Vegas, United States Duration: Dec 3 2017 → Dec 6 2017 |
Other
Other | 2017 Winter Simulation Conference, WSC 2017 |
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Country | United States |
City | Las Vegas |
Period | 12/3/17 → 12/6/17 |
ASJC Scopus subject areas
- Software
- Modeling and Simulation
- Computer Science Applications