Abstract
At-speed test of integrated circuits is becoming critical to detect subtle delay defects. Existing structural at-speed test methods are inadequate because they are unable to supply sufficiently-varied functional clock sequences to test complex sequential logic. Moreover, they require tight restrictions on the circuit design. In this paper, we present a new method for at-speed structural test of ASICs, having no tight restrictions on the circuit design. In the present implementation, any complex at-speed functional clock waveform for 16 cycles can be applied. We present DFT structures that can generate high-speed launch-off-capture as well as launch-off-scan clocking without the need to switch a scan enable at-speed. We also describe a method to test asynchronous clock domains simultaneously. Experimental results on fault coverage and hardware measurements for three multi-million gate ASICs demonstrate the feasibility of the proposed approach.
Original language | English (US) |
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Title of host publication | Proceedings - International Test Conference |
DOIs | |
State | Published - 2007 |
Externally published | Yes |
Event | 2006 IEEE International Test Conference, ITC - Santa Clara, CA, United States Duration: Oct 22 2006 → Oct 27 2006 |
Other
Other | 2006 IEEE International Test Conference, ITC |
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Country | United States |
City | Santa Clara, CA |
Period | 10/22/06 → 10/27/06 |
ASJC Scopus subject areas
- Engineering(all)