At-speed structural test for high-performance ASICs

Vikram Iyengar, Toshihiko Yokota, Kazuhiro Yamada, Theo Anemikos, Bob Bassett, Mike Degregorio, Rudy Farmer, Gary Grise, Mark Johnson, Dave Milton, Mark Taylor, Frank Woytowich

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

At-speed test of integrated circuits is becoming critical to detect subtle delay defects. Existing structural at-speed test methods are inadequate because they are unable to supply sufficiently-varied functional clock sequences to test complex sequential logic. Moreover, they require tight restrictions on the circuit design. In this paper, we present a new method for at-speed structural test of ASICs, having no tight restrictions on the circuit design. In the present implementation, any complex at-speed functional clock waveform for 16 cycles can be applied. We present DFT structures that can generate high-speed launch-off-capture as well as launch-off-scan clocking without the need to switch a scan enable at-speed. We also describe a method to test asynchronous clock domains simultaneously. Experimental results on fault coverage and hardware measurements for three multi-million gate ASICs demonstrate the feasibility of the proposed approach.

Original languageEnglish (US)
Title of host publicationProceedings - International Test Conference
DOIs
StatePublished - 2007
Externally publishedYes
Event2006 IEEE International Test Conference, ITC - Santa Clara, CA, United States
Duration: Oct 22 2006Oct 27 2006

Other

Other2006 IEEE International Test Conference, ITC
CountryUnited States
CitySanta Clara, CA
Period10/22/0610/27/06

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Iyengar, V., Yokota, T., Yamada, K., Anemikos, T., Bassett, B., Degregorio, M., Farmer, R., Grise, G., Johnson, M., Milton, D., Taylor, M., & Woytowich, F. (2007). At-speed structural test for high-performance ASICs. In Proceedings - International Test Conference [4079364] https://doi.org/10.1109/TEST.2006.297686