At-speed structural test for high-performance ASICs

Vikram Iyengar; Toshihiko Yokota; Kazuhiro Yamada; Theo Anemikos; Bob Bassett; Mike Degregorio; Rudy Farmer; Gary Grise; Mark Johnson; Dave Milton; Mark Taylor; Frank Woytowich

doi:10.1109/TEST.2006.297686

At-speed structural test for high-performance ASICs

Vikram Iyengar, Toshihiko Yokota, Kazuhiro Yamada, Theo Anemikos, Bob Bassett, Mike Degregorio, Rudy Farmer, Gary Grise, Mark Johnson, Dave Milton, Mark Taylor, Frank Woytowich

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

31 Scopus citations

Abstract

At-speed test of integrated circuits is becoming critical to detect subtle delay defects. Existing structural at-speed test methods are inadequate because they are unable to supply sufficiently-varied functional clock sequences to test complex sequential logic. Moreover, they require tight restrictions on the circuit design. In this paper, we present a new method for at-speed structural test of ASICs, having no tight restrictions on the circuit design. In the present implementation, any complex at-speed functional clock waveform for 16 cycles can be applied. We present DFT structures that can generate high-speed launch-off-capture as well as launch-off-scan clocking without the need to switch a scan enable at-speed. We also describe a method to test asynchronous clock domains simultaneously. Experimental results on fault coverage and hardware measurements for three multi-million gate ASICs demonstrate the feasibility of the proposed approach.

Original language	English (US)
Title of host publication	Proceedings - International Test Conference
DOIs	https://doi.org/10.1109/TEST.2006.297686
State	Published - 2007
Externally published	Yes
Event	2006 IEEE International Test Conference, ITC - Santa Clara, CA, United States Duration: Oct 22 2006 → Oct 27 2006

Other

Other	2006 IEEE International Test Conference, ITC
Country/Territory	United States
City	Santa Clara, CA
Period	10/22/06 → 10/27/06

ASJC Scopus subject areas

Engineering(all)

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10.1109/TEST.2006.297686

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At-speed structural test for high-performance ASICs. / Iyengar, Vikram; Yokota, Toshihiko; Yamada, Kazuhiro; Anemikos, Theo; Bassett, Bob; Degregorio, Mike; Farmer, Rudy; Grise, Gary; Johnson, Mark; Milton, Dave; Taylor, Mark; Woytowich, Frank.

Proceedings - International Test Conference. 2007. 4079364.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Iyengar, V, Yokota, T, Yamada, K, Anemikos, T, Bassett, B, Degregorio, M, Farmer, R, Grise, G, Johnson, M, Milton, D, Taylor, M & Woytowich, F 2007, At-speed structural test for high-performance ASICs. in Proceedings - International Test Conference., 4079364, 2006 IEEE International Test Conference, ITC, Santa Clara, CA, United States, 10/22/06. https://doi.org/10.1109/TEST.2006.297686

@inproceedings{cb46fe4c6b6344c1a29f6140b4caf175,

title = "At-speed structural test for high-performance ASICs",

abstract = "At-speed test of integrated circuits is becoming critical to detect subtle delay defects. Existing structural at-speed test methods are inadequate because they are unable to supply sufficiently-varied functional clock sequences to test complex sequential logic. Moreover, they require tight restrictions on the circuit design. In this paper, we present a new method for at-speed structural test of ASICs, having no tight restrictions on the circuit design. In the present implementation, any complex at-speed functional clock waveform for 16 cycles can be applied. We present DFT structures that can generate high-speed launch-off-capture as well as launch-off-scan clocking without the need to switch a scan enable at-speed. We also describe a method to test asynchronous clock domains simultaneously. Experimental results on fault coverage and hardware measurements for three multi-million gate ASICs demonstrate the feasibility of the proposed approach.",

author = "Vikram Iyengar and Toshihiko Yokota and Kazuhiro Yamada and Theo Anemikos and Bob Bassett and Mike Degregorio and Rudy Farmer and Gary Grise and Mark Johnson and Dave Milton and Mark Taylor and Frank Woytowich",

year = "2007",

doi = "10.1109/TEST.2006.297686",

language = "English (US)",

isbn = "1424402921",

booktitle = "Proceedings - International Test Conference",

note = "2006 IEEE International Test Conference, ITC ; Conference date: 22-10-2006 Through 27-10-2006",

}

TY - GEN

T1 - At-speed structural test for high-performance ASICs

AU - Iyengar, Vikram

AU - Yokota, Toshihiko

AU - Yamada, Kazuhiro

AU - Anemikos, Theo

AU - Bassett, Bob

AU - Degregorio, Mike

AU - Farmer, Rudy

AU - Grise, Gary

AU - Johnson, Mark

AU - Milton, Dave

AU - Taylor, Mark

AU - Woytowich, Frank

PY - 2007

Y1 - 2007

N2 - At-speed test of integrated circuits is becoming critical to detect subtle delay defects. Existing structural at-speed test methods are inadequate because they are unable to supply sufficiently-varied functional clock sequences to test complex sequential logic. Moreover, they require tight restrictions on the circuit design. In this paper, we present a new method for at-speed structural test of ASICs, having no tight restrictions on the circuit design. In the present implementation, any complex at-speed functional clock waveform for 16 cycles can be applied. We present DFT structures that can generate high-speed launch-off-capture as well as launch-off-scan clocking without the need to switch a scan enable at-speed. We also describe a method to test asynchronous clock domains simultaneously. Experimental results on fault coverage and hardware measurements for three multi-million gate ASICs demonstrate the feasibility of the proposed approach.

AB - At-speed test of integrated circuits is becoming critical to detect subtle delay defects. Existing structural at-speed test methods are inadequate because they are unable to supply sufficiently-varied functional clock sequences to test complex sequential logic. Moreover, they require tight restrictions on the circuit design. In this paper, we present a new method for at-speed structural test of ASICs, having no tight restrictions on the circuit design. In the present implementation, any complex at-speed functional clock waveform for 16 cycles can be applied. We present DFT structures that can generate high-speed launch-off-capture as well as launch-off-scan clocking without the need to switch a scan enable at-speed. We also describe a method to test asynchronous clock domains simultaneously. Experimental results on fault coverage and hardware measurements for three multi-million gate ASICs demonstrate the feasibility of the proposed approach.

UR - http://www.scopus.com/inward/record.url?scp=39749176233&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=39749176233&partnerID=8YFLogxK

U2 - 10.1109/TEST.2006.297686

DO - 10.1109/TEST.2006.297686

M3 - Conference contribution

SN - 1424402921

SN - 9781424402922

BT - Proceedings - International Test Conference

T2 - 2006 IEEE International Test Conference, ITC

Y2 - 22 October 2006 through 27 October 2006

ER -

At-speed structural test for high-performance ASICs

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