An integrated framework for at-speed and ATE-driven delay test of contract-manufactured ASICs

Vikram Iyengar, Kenneth Pichamuthu, Andy Ferko, Frank Woytowich, Dave Lackey, Gary Grise, Mark Taylor, Mike Degregorio, Steve Oakland

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

In contract manufacturing, the circuit netlist is owned by the ASIC customer. The manufacturer is required to work strictly within the design structure established by the customer. To manufacture high-quality components in this environment, it is critical to meet the customer's mandated quality and performance criteria, while minimizing hardware overhead and introducing litle orno design change. In this paper, we present a test framework for contract-manufactured ASICs using low-cost testers. Key aspects of the framework are low hardware overhead, significant savings in test data volume and test cost, and tight integration of the at-speed and ATE-driven test components to the design and manufacturing process.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE VLSI Test Symposium
Pages173-178
Number of pages6
DOIs
StatePublished - 2007
Externally publishedYes
Event25th IEEE VLSI Test Symposium, VTS'07 - Berkeley, CA, United States
Duration: May 6 2007May 10 2007

Other

Other25th IEEE VLSI Test Symposium, VTS'07
CountryUnited States
CityBerkeley, CA
Period5/6/075/10/07

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Iyengar, V., Pichamuthu, K., Ferko, A., Woytowich, F., Lackey, D., Grise, G., Taylor, M., Degregorio, M., & Oakland, S. (2007). An integrated framework for at-speed and ATE-driven delay test of contract-manufactured ASICs. In Proceedings of the IEEE VLSI Test Symposium (pp. 173-178). [4209908] https://doi.org/10.1109/VTS.2007.15