Adaptive testing - Cost reduction through test pattern sampling

Matt Grady; Bradley Pepper; Joshua Patch; Michael Degregorio; Phil Nigh

doi:10.1109/TEST.2013.6651891

Adaptive testing - Cost reduction through test pattern sampling

Matt Grady, Bradley Pepper, Joshua Patch, Michael Degregorio, Phil Nigh

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Scopus citations

Abstract

In this paper, we will present two different applications of 'test pattern sampling' for logic testing that have significantly improved test cost for Processors and SOCs/ASICs at IBM. The drivers and implementations for these two methods were completely different - one relying on real-time analysis/optimization applied at wafer test; the other based on off-line analysis with daily updates and real-time adjustments at Final Test.

Original language	English (US)
Title of host publication	Proceedings - International Test Conference
DOIs	https://doi.org/10.1109/TEST.2013.6651891
State	Published - 2013
Externally published	Yes
Event	44th IEEE International Test Conference, ITC 2013 - Anaheim, CA, United States Duration: Sep 10 2013 → Sep 12 2013

Other

Other	44th IEEE International Test Conference, ITC 2013
Country	United States
City	Anaheim, CA
Period	9/10/13 → 9/12/13

ASJC Scopus subject areas

Electrical and Electronic Engineering
Applied Mathematics

Access to Document

10.1109/TEST.2013.6651891

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Cite this

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title = "Adaptive testing - Cost reduction through test pattern sampling",

abstract = "In this paper, we will present two different applications of 'test pattern sampling' for logic testing that have significantly improved test cost for Processors and SOCs/ASICs at IBM. The drivers and implementations for these two methods were completely different - one relying on real-time analysis/optimization applied at wafer test; the other based on off-line analysis with daily updates and real-time adjustments at Final Test.",

author = "Matt Grady and Bradley Pepper and Joshua Patch and Michael Degregorio and Phil Nigh",

year = "2013",

doi = "10.1109/TEST.2013.6651891",

language = "English (US)",

isbn = "9781479908592",

booktitle = "Proceedings - International Test Conference",

note = "44th IEEE International Test Conference, ITC 2013 ; Conference date: 10-09-2013 Through 12-09-2013",

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AU - Patch, Joshua

AU - Degregorio, Michael

AU - Nigh, Phil

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AB - In this paper, we will present two different applications of 'test pattern sampling' for logic testing that have significantly improved test cost for Processors and SOCs/ASICs at IBM. The drivers and implementations for these two methods were completely different - one relying on real-time analysis/optimization applied at wafer test; the other based on off-line analysis with daily updates and real-time adjustments at Final Test.

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DO - 10.1109/TEST.2013.6651891

M3 - Conference contribution

AN - SCOPUS:84891513959

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T2 - 44th IEEE International Test Conference, ITC 2013

Y2 - 10 September 2013 through 12 September 2013

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