Adaptive testing - Cost reduction through test pattern sampling

Matt Grady; Bradley Pepper; Joshua Patch; Michael Degregorio; Phil Nigh

doi:10.1109/TEST.2013.6651891

Adaptive testing - Cost reduction through test pattern sampling

Matt Grady, Bradley Pepper, Joshua Patch, Michael Degregorio, Phil Nigh

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

In this paper, we will present two different applications of 'test pattern sampling' for logic testing that have significantly improved test cost for Processors and SOCs/ASICs at IBM. The drivers and implementations for these two methods were completely different - one relying on real-time analysis/optimization applied at wafer test; the other based on off-line analysis with daily updates and real-time adjustments at Final Test.

Original language	English (US)
Title of host publication	Proceedings - International Test Conference
DOIs	https://doi.org/10.1109/TEST.2013.6651891
State	Published - 2013
Externally published	Yes
Event	44th IEEE International Test Conference, ITC 2013 - Anaheim, CA, United States Duration: Sep 10 2013 → Sep 12 2013

Other

Other	44th IEEE International Test Conference, ITC 2013
Country	United States
City	Anaheim, CA
Period	9/10/13 → 9/12/13

Fingerprint

Adaptive Testing

Application specific integrated circuits

Cost reduction

Sampling

Testing

Costs

Real-time

Wafer

Driver

Adjustment

Update

Logic

Optimization

Line

ASJC Scopus subject areas

Electrical and Electronic Engineering
Applied Mathematics

Cite this

Grady, M., Pepper, B., Patch, J., Degregorio, M., & Nigh, P. (2013). Adaptive testing - Cost reduction through test pattern sampling. In Proceedings - International Test Conference [6651891] https://doi.org/10.1109/TEST.2013.6651891

Adaptive testing - Cost reduction through test pattern sampling. / Grady, Matt; Pepper, Bradley; Patch, Joshua; Degregorio, Michael; Nigh, Phil.

Proceedings - International Test Conference. 2013. 6651891.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Grady, M, Pepper, B, Patch, J, Degregorio, M & Nigh, P 2013, Adaptive testing - Cost reduction through test pattern sampling. in Proceedings - International Test Conference., 6651891, 44th IEEE International Test Conference, ITC 2013, Anaheim, CA, United States, 9/10/13. https://doi.org/10.1109/TEST.2013.6651891

Grady M, Pepper B, Patch J, Degregorio M, Nigh P. Adaptive testing - Cost reduction through test pattern sampling. In Proceedings - International Test Conference. 2013. 6651891 https://doi.org/10.1109/TEST.2013.6651891

Grady, Matt ; Pepper, Bradley ; Patch, Joshua ; Degregorio, Michael ; Nigh, Phil. / Adaptive testing - Cost reduction through test pattern sampling. Proceedings - International Test Conference. 2013.

@inproceedings{1b7b525314f24e9796019fee305a4a84,

title = "Adaptive testing - Cost reduction through test pattern sampling",

abstract = "In this paper, we will present two different applications of 'test pattern sampling' for logic testing that have significantly improved test cost for Processors and SOCs/ASICs at IBM. The drivers and implementations for these two methods were completely different - one relying on real-time analysis/optimization applied at wafer test; the other based on off-line analysis with daily updates and real-time adjustments at Final Test.",

author = "Matt Grady and Bradley Pepper and Joshua Patch and Michael Degregorio and Phil Nigh",

year = "2013",

doi = "10.1109/TEST.2013.6651891",

language = "English (US)",

isbn = "9781479908592",

booktitle = "Proceedings - International Test Conference",

}

TY - GEN

T1 - Adaptive testing - Cost reduction through test pattern sampling

AU - Grady, Matt

AU - Pepper, Bradley

AU - Patch, Joshua

AU - Degregorio, Michael

AU - Nigh, Phil

PY - 2013

Y1 - 2013

N2 - In this paper, we will present two different applications of 'test pattern sampling' for logic testing that have significantly improved test cost for Processors and SOCs/ASICs at IBM. The drivers and implementations for these two methods were completely different - one relying on real-time analysis/optimization applied at wafer test; the other based on off-line analysis with daily updates and real-time adjustments at Final Test.

AB - In this paper, we will present two different applications of 'test pattern sampling' for logic testing that have significantly improved test cost for Processors and SOCs/ASICs at IBM. The drivers and implementations for these two methods were completely different - one relying on real-time analysis/optimization applied at wafer test; the other based on off-line analysis with daily updates and real-time adjustments at Final Test.

UR - http://www.scopus.com/inward/record.url?scp=84891513959&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84891513959&partnerID=8YFLogxK

U2 - 10.1109/TEST.2013.6651891

DO - 10.1109/TEST.2013.6651891

M3 - Conference contribution

AN - SCOPUS:84891513959

SN - 9781479908592

BT - Proceedings - International Test Conference

ER -

Access to Document

10.1109/TEST.2013.6651891