Adaptive testing - Cost reduction through test pattern sampling

Matt Grady, Bradley Pepper, Joshua Patch, Michael Degregorio, Phil Nigh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

In this paper, we will present two different applications of 'test pattern sampling' for logic testing that have significantly improved test cost for Processors and SOCs/ASICs at IBM. The drivers and implementations for these two methods were completely different - one relying on real-time analysis/optimization applied at wafer test; the other based on off-line analysis with daily updates and real-time adjustments at Final Test.

Original languageEnglish (US)
Title of host publicationProceedings - International Test Conference
DOIs
StatePublished - 2013
Externally publishedYes
Event44th IEEE International Test Conference, ITC 2013 - Anaheim, CA, United States
Duration: Sep 10 2013Sep 12 2013

Other

Other44th IEEE International Test Conference, ITC 2013
CountryUnited States
CityAnaheim, CA
Period9/10/139/12/13

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Applied Mathematics

Cite this

Grady, M., Pepper, B., Patch, J., Degregorio, M., & Nigh, P. (2013). Adaptive testing - Cost reduction through test pattern sampling. In Proceedings - International Test Conference [6651891] https://doi.org/10.1109/TEST.2013.6651891