Adaptive testing - Cost reduction through test pattern sampling

Matt Grady, Bradley Pepper, Joshua Patch, Michael Degregorio, Phil Nigh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations


In this paper, we will present two different applications of 'test pattern sampling' for logic testing that have significantly improved test cost for Processors and SOCs/ASICs at IBM. The drivers and implementations for these two methods were completely different - one relying on real-time analysis/optimization applied at wafer test; the other based on off-line analysis with daily updates and real-time adjustments at Final Test.

Original languageEnglish (US)
Title of host publicationProceedings - International Test Conference
StatePublished - 2013
Externally publishedYes
Event44th IEEE International Test Conference, ITC 2013 - Anaheim, CA, United States
Duration: Sep 10 2013Sep 12 2013


Other44th IEEE International Test Conference, ITC 2013
Country/TerritoryUnited States
CityAnaheim, CA

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Applied Mathematics


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