Abstract
In this paper, we will present two different applications of 'test pattern sampling' for logic testing that have significantly improved test cost for Processors and SOCs/ASICs at IBM. The drivers and implementations for these two methods were completely different - one relying on real-time analysis/optimization applied at wafer test; the other based on off-line analysis with daily updates and real-time adjustments at Final Test.
Original language | English (US) |
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Title of host publication | Proceedings - International Test Conference |
DOIs | |
State | Published - 2013 |
Externally published | Yes |
Event | 44th IEEE International Test Conference, ITC 2013 - Anaheim, CA, United States Duration: Sep 10 2013 → Sep 12 2013 |
Other
Other | 44th IEEE International Test Conference, ITC 2013 |
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Country | United States |
City | Anaheim, CA |
Period | 9/10/13 → 9/12/13 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Applied Mathematics